How to configure SDRAM for HPS ?

[rshal2]

Hello,

Is SDRAM configuration for a custom board should be done in Qsys ?

I found the following which confused me if it should be done in qsys or not:

https://forums.intel.com/s/question/0D50P00003yySBlSAM/de1soc-sdram-timing-parameters-for-qsys

The other question I would like to ask, should it be configured according to sdram datasheet or other method ?

Thanks

[Fawaz_Al-Jubori]

Hello,

Qsys would be the place to configure the DDR of the HPS.

In the HPS component of Qsys, you will see a tab called "SDRAM". This tab is used to configure the SDRAM of the FPGA.

The forum thread you mentioned about meant to say no need to add DDR3 IP as a separate component inside qsys. This would be done only when targeting FPGA DDR.

Thanks

[rshal2]

Thank you!

Is the right way to configure the timing should be by using ddr datasheet, or is it that the default parameters are in qsys should be sufficient ?

Thanks

[sstrell · Accepted solution]

Timing constraints for most IP, including memory interfaces, are set up automatically when you generate the IP. You still need to provide constraints for clocks that drive your FPGA logic, but constraints for the IP itself are handled for you.

Important side note: the tool is no longer called Qsys. It is now called Platform Designer. It still uses .qsys files, but you won't find the tool if you're looking for Qsys.

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