Hi everyone,I'm currently working on my end of degree project at university which is about using a MAX10 FPGA for Closed-loop Control Systems. The thing is that in order to make it work, I need to be able to select the sampling instant of the ADC so I can sample whenever I want. I've been using Qsys, but it only gives you the option to select the sampling rate. I want it to sample when I wish. I think that it probably has something to do with the way you use the different signals that Qsys automatically generates once you configure your ADC and add it to the project: command_valid, command_ready, start_of_packet, end_of_packet, response_valid, response_data... and so on. I would be very grateful if you could help me with this. ;) Just for reference, I'm using: -A MAX10 10M50DAF484C7G -DE10-Lite Board Thank you in advance!
You can either filter all the sampled data to what you want or if you've enabled the slave interface on the core, simply tell it to stop running when you don't want it to. Run/stop is bit 0 in the command register, address offset 0x0.