We use 10AX057H3F34E2SG, one PCIe x8 GEN3.0 link connect to PC's PCIe node. PC will provide one PCIe Reference clock 100MHZ.
Since each GXB bank contains 6 transceiver-channels, TWO GXB Banks will be used, such as 6+2 or 4+4 channels.
Question: How could we connect one PCIe REF clock to TWO GXB Banks's dedicated REFCLK pins? Or is it OK to connect PCIe REF clock to either one of the 2 GXB Banks ?
and where could we found this information on Intel's Documentation?
I think you are correct.
I just read on UG-01143 section 3.2.4, "The reference clock network distributes a reference clock source to either the entire left or right side of the FPGA where the transceivers reside. This allows any reference lock pin to drive any transmitter PLL on the same side of the device. Designs using multiple transmitter PLLs which require the same reference clock frequency and are located along the same side of the device, can share the same dedicated reference clock (refclk) pin" .
This is where I get confirmed from official documents that only one reference clock is needed, and can be connected to either GXB banks for x8 PCIe. Thanks for answer!
Hi Nathan, if you are convenient, could you please kindly help take a look at following question? Thanks again!