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How to constrain a ADC input to a narrow delay window Arria 10

New Contributor II

I have an external ADC which I need to sample with an internally generated clock.  Reasons.  The ADC data conversion is driven by a clock I output, and I would like to sample it with a derived clock at some phase angle.  

To do this reliably, I need to be able to constrain both the output clock and the input data paths to some known delay window.  At first blush it looks like set_max_delay and set_min_delay would do the trick, but those directives seem to be aimed at setup and hold time respectively, which is not what I want.  I simply want to control the routing so that the delay is known (and repeatable).


I can set skew, which is nice, but I still need to constrain the delay time.

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2 Replies
New Contributor II

Never mind.  Did some more reading and set up a proper input delay

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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Ven Ting

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

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