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How to constrain the transceiver Rx data path?

zhenge
New Contributor I
993 Views

Dear support,

I used to only constrain XCVR with the reference  clock and expect the Quartus tool to derive all the generated constraints.

Recently I found adding logics to the Rx data path is causing timing failure, and the path is not constrained.

Leaving this path unconstrained, please let me know if this is intentional or I am missing something from my project.

report_timing -from [get_keepers {my_mdl:\My_Rx:0:My_Rx_Serdes|My_Rx_Serdes_altera_xcvr_native_a10_221_2q4miaq:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm3:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm3:inst_twentynm_pcs|gen_twentynm_hssi_rx_pld_pcs_interface.inst_twentynm_hssi_rx_pld_pcs_interface~pld_rx_data_fifo.reg}] -setup -npaths 10 -detail full_path -panel_name {Report Timing} -multi_corner
Report Timing: No setup paths were found
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Nurina
Employee
900 Views

Hello,


How about sharing through email?

I'm dropping you an email, you may send your design through there.


The reason I am requesting your design is to check if the connection/usage of the IP is correct. From there, we can tell if it is a usage problem or timing constraint problem.


Regards,

Nurina


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6 Replies
Nurina
Employee
938 Views

Hi,


Thank you for using Intel Communities.

Please allow some time while I investigate your problem.


In the meantime can you confirm that you are using the XCVR on Arria 10 device?


Thanks,

Best regards,

Nurina


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Nurina
Employee
925 Views

Hi,


Can you also share the .qar file of your project?

To generate this, go to Project>Archive Project.


Thanks,

Regards,

Nurina


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zhenge
New Contributor I
918 Views

Hi Nurina,

 

Thanks for your attention. I can't share the actual project due to IP consideration.

The part I am using is: 10AX048K4F35E3LG

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Nurina
Employee
901 Views

Hello,


How about sharing through email?

I'm dropping you an email, you may send your design through there.


The reason I am requesting your design is to check if the connection/usage of the IP is correct. From there, we can tell if it is a usage problem or timing constraint problem.


Regards,

Nurina


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zhenge
New Contributor I
879 Views

Hi Nurina,

 

Thanks for the offer, I've resolved the issue by adding immediate register at the XCVR.output.fifo with rx_clk.

The actual design is under Export Control, so I can not share easily.

Please give me your email, I'd be happy to carry on discussion with code snippet and timing reports.

I'll mark "Resolved" here.

Thanks,

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Nurina
Employee
837 Views

Hi,


I've dropped you an email, you can reply to it with your code snippet.

I’m glad that your problem is solved, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

 

If any answer from the community or Intel Support are helpful, feel free to rank your support experience by rating 4/5 survey. Please let me know of any inconvenience so that I may improve your future service experience.

 

Have a great day!


Best regards,

Nurina W.


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