Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20680 Discussions

How to deal with ADC pins of MAX10

RLee42
Novice
457 Views

It's my first time to use MAX10 ADC so I'm not sure whether my design can work.

What I have already done is generated an ADC core and also a PLL core connected with it. On my PCB, the analog signals to be measured have already been connected to the ADC pins of MAX10 on BANK1A.

However, I don't what kind of restrictions are needed for these ADC pins? Should I just simply leave these pins unused in the top module of my project or should I add some restrictions, like "reserved as input tri-stated" in assignment edit to let Quartus know these pins are allocated for ADC?

0 Kudos
1 Solution
JonWay_C_Intel
Employee
445 Views

Hi @RLee42 

You don't have to assign the ADC input pins. You only need to assign the clock and reset pins for the ADC IP. You may refer to the how to video: https://www.youtube.com/watch?v=0oO1RFa-4Xk

Hope this helps.

 

 

View solution in original post

0 Kudos
1 Reply
JonWay_C_Intel
Employee
446 Views

Hi @RLee42 

You don't have to assign the ADC input pins. You only need to assign the clock and reset pins for the ADC IP. You may refer to the how to video: https://www.youtube.com/watch?v=0oO1RFa-4Xk

Hope this helps.

 

 

0 Kudos
Reply