How to disable multiple reconfiguration profile when I only use one of them?

[vfraloo]

Hi,

I'm using 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP to implement 1G Ethernet. I choose the external PHY to MGBASE-T, and the PHY speed is 1G/2.5G. There are two reconfiguration profile for two PHY speed. How could I to disable the 2.5G reconfiguration profile, because I don't need it. Another important reason is that I connect an IOPLL after tx_clkout which use as reference clock, Quartus report a warning below, and the timing constraint for the output clock of IOPLL can not be derived automatically.

"

The master clock for this clock assignment could not be derived.

Clock: xxx|alt_mge_phy_0|profile0|tx_clkout|ch0 found as a potential master clock candidate

Clock: xxx|alt_mge_phy_0|profile1|tx_clkout|ch0 found as a potential master clock candidate

"

So I think if I can disable 2.5G reconfiguration profile, It will solve my problem.

[Paveetirra_Srie]

Hi Rain Bow,

To change the PHY speed, kindly use the reconfiguration block in the MAC+PHY example design.

For more detailed steps, refer to Multi rate Ethernet UG page 21 4.3. Switching Operation Speed :

https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/10g-multirate-ethernet-phy.html

When you configure the PHY in 1G/2.5G configuration, Intel recommends that you add the following constraint in the timing constraint file. Kindly refer to page 20 for the Timing Constraint.

Regards,

Pavee

[vfraloo]

Hi,

I'm not trying to know how to switch speed, I only want to know how to disable Quartas analyze timing for 2.5G speed,  1G is enough for my design.

Thanks.

[Paveetirra_Srie]

Hi Rain Bow,

Apologize for the delay and also misinterpretation on your issue. Please give me sometime to investigate this issue and will get back to you with updates.

Regards,

Pavee

[Paveetirra_Srie]

Hi rain Bow,

Apologize for the delay.

Transceiver PHY dynamic reconfiguration interface—an Avalon-MM interface to read and write the Intel Stratix 10 Native PHY IP core registers. This interface supports dynamic reconfiguration of the transceiver. It is used to configure the transceiver operating modes to switch to desired Ethernet operating speeds. I believe you cant disable it but instead you can switch it.

Regards,

Pavee

[Paveetirra_Srie]

Hi Rain Bow,

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.