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Altera_Forum
Honored Contributor I
793 Views

How to ignore Latches for Timing analysis

Hi , 

 

I have latches (as combinational loops) which must be used in my design. These latches acts as start/end point for timing analysis.  

So my design is not getting properly optimized. 

 

Is there any way, i can ignore these latches from timing analysis & for synthesis/Fitter optimizations. 

I have tried False path/ disable timing constraints and it didn't work. Also tried switch -no_latch for timing but its not useful. 

 

Regards, 

NKD
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Altera_Forum
Honored Contributor I
44 Views

Hello , 

 

Can I guide tool to ignore latches as sequential elements. Either in synthesis or Fitter stage. 

 

Regards, 

NKD
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