How to implement DSP operations

[Altera_Forum]

Hello, 

 I am quite new to FPGAs so forgive me if this is a blatant question.  I need to implement a mathematical function ( a/ln( (b / (c - d)) +e ) ), where c is my input, the others are constants, and all the values are floating point. I have looked at the arithmetical libraries in quartus and it is possible with them, however I have seen at multiple places that using DSPs(which I understood as hardware mathematical blocks) is much faster and resource efficient. I have had a look at the Nios II Floating Point Hardware Component User Guide, but there it connects it to a Nios processor and I still am quite confused about how to set what instructions the module actually executes, I cannot really find where to set it in the parameters either.  Am I interpreting the function of DSPs wrong or have I missed a user guide? I was planning to implement the part inside the logarithm inside a DSP, and the other parts with arithm blocks(as DSPs don't have a natural logarithm function).  The input would be a continous data stream, so using components that would need a slower clock(and/or some ready-ack logic) to function overall instead of pipelining would not really suit me.  Best regards, Tibor

[Altera_Forum]

--- Quote Start ---  Hello,  I am quite new to FPGAs so forgive me if this is a blatant question.  I need to implement a mathematical function ( a/ln( (b / (c - d)) +e ) ), where c is my input, the others are constants, and all the values are floating point. I have looked at the arithmetical libraries in quartus and it is possible with them, however I have seen at multiple places that using DSPs(which I understood as hardware mathematical blocks) is much faster and resource efficient. I have had a look at the Nios II Floating Point Hardware Component User Guide, but there it connects it to a Nios processor and I still am quite confused about how to set what instructions the module actually executes, I cannot really find where to set it in the parameters either.  Am I interpreting the function of DSPs wrong or have I missed a user guide? I was planning to implement the part inside the logarithm inside a DSP, and the other parts with arithm blocks(as DSPs don't have a natural logarithm function).  The input would be a continous data stream, so using components that would need a slower clock(and/or some ready-ack logic) to function overall instead of pipelining would not really suit me.  Best regards, Tibor  --- Quote End ---    if your inputs are constant all except one then a table(LUT) of pre-calculated output will do best assuming memory requirement/resolution of result are acceptable to you