How to implement <line buffer> in the avalon-stream to connect other VIP cores?

[idemosaic]

目前，我们想添加自己的IP核来对接官方的VIP核。

然后自己的算法需要缓存3行，有没有这方面的参考代码或建议呢？希望不吝赐教！

[ZH_Intel]

Hi idemosaic,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi idemosaic,

Thank you for your patience.

The VIP handles the video with frame unit, no line buffer.

You may need to identify the link number by counting the sync signal.

At the moment, there are no reference code available for this.

However, you may refer to the Intel FPGA Design Store for some VIP reference design that might help.

Intel FPGA Design Store 

Thank you.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi idemosaic,

Good day.

I wish to follow up with you about this case.

Do you still have further inquiries on this case?

Hoping to hear back from you so that we can proceed for next step.

Thank you.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi idemosaic,

Good day.

I wish to follow up with you about this case.

Do you still have further inquiries on this case?

We hope that the last note clears up this matter.

I will remain this loop open for 2 days.

If we do not receive any response from you to the previous answer that I have provided. 

This thread will be transitioned to community support. 

Thank you.

Best Regards,

ZulsyafiqH_Intel

[ZH_Intel]

Hi idemosaic,

Good day.

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you.

Best Regards,

ZulsyafiqH_Intel