How to insert pixel values?

[Altera_Forum]

I am new in VHDL and i am currently working on my diploma thesis which is about hardware implementation of a neural network that does face detection using viola-jones algorithm.My question is that i want to insert a window(let's say 20x20 pixels).So i want to know which is the most efficient way to insert the values of the pixels serially(one by one).I think of making an 2 dimensional array but it uses a lot of pins.As i said before i am new in VHDL so please understand my lack of knowledge.Thanks in advance. 

  PS. The value of each pixel would be an std_logic_vector or bit_vector since the image would be in grayscale mode.

[Altera_Forum]

yes you could use a 2-dimensional array: 

 type PIXEL_TYPE is array (natural range 0 to 19) of std_logic_vector(19 downto 0); signal pixel_array: PIXEL_TYPE;  You can access each pixel in that array with pixel_array(i)(j). You have to increment i with every pixel clock, j with every line.  Which hardware you are using? Sensor? FPGA? Devkit? May be it's better to store the pixel values in internal RAM. How does your algorithm work? Local in a small region or global (whole image)?  Jens

[Altera_Forum]

First of all i would like to thank you for your quick reply.I think that in your example code you define an 1 dimensional array and not a 2 dimensional.To define a 2 dimensional i think that you have to write it like this(if i am right): 

type PIXEL_TYPE is array (natural range 0 to 19,natural range 0 to 19) of std_logic_vector(19 downto 0); signal pixel_array: PIXEL_TYPE; I am using FPGA.My algorithm is about to make a hardware implementation of a neuron(the main part of a neural network). I would like to insert a window of the whole image each time.For example if the whole image is 400x400 pixels i would like to insert to the neuron a 20x20 window.

[Altera_Forum]

oh yes you are right, I just forgot the second declaration, (it would be right if you have just one Bit per Pixel :) ) What I want to tell you was: 

 type ROW_TYPE is array (natural range 0 to 19) of std_logic_vector(19 downto 0); type PIXEL_TYPE is arry (natural range 0 to 19) of ROW_TYPE;  signal pixel_array: PIXEL_TYPE;  With my question about the hardware I meant which FPGA, which sensor, which devkit (or custom hw) you are using?  If you have an 400x400 image (20 bits per pixel) where does it comes from? You can't store the whole image in internal logic so you have to load the 20x20 window each time you need it. Assuming that you have an external RAM with 32-bit data bus than loading needs 250 clock cycles.  Jens

[Altera_Forum]

So i declare an 2 dimensional array as it mentioned before.I assume that i need 20 signals,each of one for each row of pixels.So lets say i have x1,x2,....x20 signals and every clock cycle i will insert a value for its pixel.Am i right?Thanks in advance

[Altera_Forum]

I don't know much about neural networks, but do you want the image to be displayed on a screen or something? I have only worked with Cyclone II and VGA screens, using a video DAC. If you have any fancy screen controller, than I think you need to read in it's manuals. If you, as I, want to show an image on a VGA screen, using nothing but a suitable DAC, you have to control all synch signals and simply send out your grayscale value when the pixel counter passes your 20x20-pixel-window.

[Altera_Forum]

Forget about neural networks(it was only mentioned for informational reasons).All i want to do is to write an appropriate code in VHDL that will be synthesizable.So were my thoughts in the previous post about the implementation right?

[Altera_Forum]

What will happen if you declare the signal pixel_array : PIXEL_TYPE as you described is that you get 400 vectors with 20 D-flip-flops each in your FPGA (which should result in 8000 DFF in 4000 ALMs, if you are using Stratix II FPGAs). 

I must admit I mess up everything about the window and what Jens said about external RAM. If you keep those 8000 DFF within the FPGA, you can assign all of them within the same clock cycle if you want. If you keep them in a 32 bits wide memory, you can access one pixel per clock cycle. If you send them serially to a VGA connector, you must send one pixel per clock cycle. If you think of you design as a hardware solution, and then think of the VHDL code as a way of explaining for the compiler what you think of, your solution will always be synthesizable. Do you want to send this window to a monitor?

[Altera_Forum]

No i dont want to send this window to a monitor.I just want to insert the window and do some operations(add,sub) between some specific pixels(values).That's all.I thought of the way i will insert the window.It is something like this(lets say the windows size is 16x16) : 

PORT( x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16 : IN UNSIGNED(7 DOWNTO 0); I declare 16 inputs.Every one of them will change its value at every clock cycle. Then i declare 16 1dimensional arrays.Every one will store every row of the window.After 16 clock cycles the window will be inserted.Something like this :  TYPE row IS ARRAY(1 TO 24) OF UNSIGNED(7 DOWNTO 0);  VARIABLE row1,row2,row3,row4,row5,row6,row7,row8,row9,row10,row11,row12,row13,row14,row15,row16 : row;

[Altera_Forum]

did you read up on digital logic yet? I guess you didnt.