How to place constraint one path from register output to IO pin so the routing does not change the next time I compile. Please see case 00333897.

[MTAWA]

I have critical io timing to external device. It is presently working well with time constraints. However, I want to place constrain it so it does not change when I recompile. Please refer to case 00333897​

[GuaBin_N_Intel]

You can set that specific output register at IO block​. It is the fastest and dedicated path connected to IO buffer.  Kindly find the setting in assignment editor and follow what had explained here https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_output_register.htm 

[MTAWA]

Thanks GNg, I am familiar with using the assignment editor to place register in the IOB.;  I probably used a bad example, but I would like to know how to placement constraint a path, say register to register with critical timing in-between them.  Thank you.

[GuaBin_N_Intel]

In general, we would use overconstraint method to tell Fitter putting more priority on specific path during placement. Use "set_max_delay" in SDC as in example here https://fpgawiki.intel.com/wiki/Timing_Constraints to get higher Fmax of a path.

[MTAWA]

Thanks again GNg, I am familiar with timing constraints and max delay and min delays. I'm looking for placement constraints of a path, similar to floorplanning, but focused on a single path.​

[GuaBin_N_Intel]

​Yes, placement constraint can be made on certain ALM location but there's no method for routing within a path.  Find "location" and then set coordination of a register or LAB https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_qsf_reference.pdf

[MTAWA]

​GNg the link provided above is for advanced timing constraints.