How to prevent the synthesizer from optimizing signals away? Fanout?

[MGrab6]

Using:

5M570 Max V CLPD speed grade 5.

CLK_IN is and in port

div_clk(3 downto 0) is a signal

I have a clock that is derived from a counter to provide divide by 4 functionality, and other prescaler divisions. An input clock CLK_IN is on one of the dedicated clock pins and is synthesized to a global clock in the fitter report. The div_cnt(1) is dividing by 4 and is also used for a clock with a fanout of 129. This is also assigned to a global clock and verified via the fitter after synthesis.

The TimeQuest analyzer is giving me Fmax=17.75MHz for div_cnt(1) and Fmax CLK_IN=238.1MHz. div_cnt(3) has an Fmax=105.3MHz fanout of 6 also a global clock.

If I change all instances of div_cnt(1) in all they processes with CLK_IN TimeQuest gives Fmax=24.23MHz also with a fanout of 129.

I suspect the slow time of the div_cnt(1) signal is due to the large fanout. The same design was faster with the CLK_IN with the same fanout.

- Is there a buffer issue with the way the div_clk(1) is connected to the global clock bus? It is verified via the fitter that it is a global clock.

- The Max V does not appear to have a PLL or ALTCLKCTRL megafunction?

- Attempts to buffer it they synthesizer just get deleted by the synthesizer. I have one remaining global clock, is there a way to assign the same signal more than one global clock, I can balance the fanout manually by using the two clocks for different process?

I'd be happy with any other suggestions. I have plenty of space left on the device.

[Kenny_Tan]

can you attached your design.qar to have a look? Basically, high fan out should not be a issue as you are using global routing. But, it might pull your whole circuit into one side if your frequencies requirement are high.

We need to look into the timing analyzer in order to further analyze the root cause.

[MGrab6]

Quartus II is generating the timing analysis. Is there a way to export directly to a .qar file? I have attached the report file form Quartus II. Please advise on how to get a .qar.

I did some floor planning of the logic elements manually and that seemed to help as it was placing some of the fast counters all over the place. I moved them close to the outputs and very near each other, and it helped. I intend to do more of this but tried to get a dual clock running first.

I wanted to just use 2 of the 4 clock lines and balance the usage manually but I can't find the option to force it no not optimize the second identical signal out.

[Kenny_Tan]

You can archive the project to *.qar by project -> archive project.

Looking into the report files, I cannot see high fan out on the node.

What I suggest is do it on the RTL itself. You can control how much fan out you want to a particular module. This way, you can use different pll if needed for fan out issue.

[MGrab6]

I did not think the MAX V had a PLL? I haven't played with the RTL view much. Although it seems far more intuitive. I take it the 12{1} means 12 of div_counter[1] into that logic block? Mark

[MGrab6]

Is there documentation on how to directly edit the RTL in Quartus II? I can get to the RTL viewer but can't make modificatoins there.

[MGrab6]

These two includes at the top worked. library altera; use altera.altera_syn_attributes.all; Along with the VHDL: attribute keep : boolean; attribute keep of MASTER_CLK : signal is true; attribute keep of MASTER_CLK1 : signal is true; This preserved the two clock signals. I had omitted the “library altera;” when trying this earlier. Increasing fmax and how: Varying which version of master clock each process received yielded a few MHz improvement in fmax. Greater improvement was realized by assigning logic to specific areas, aka floor planning. The devices assignment window and qsf file was used for this, but this only yielded an fmax of 21Mhz. The greatest benefit came from use of the Tools>Advisors>Timing optimization advisor. Timing Optimization Advisor: Setting “Placement Effort Multiplier” to 4 and, Setting “Fitting Initial Placement Seed” from 40-50 Achieved an fmax of 29Mhz, and a little bit more fiddling with which master clock each process used yeilded 31Mhz. I see you can use the Design Space Explorer to vary the seed starting point to optimize a design. I'll try that next. I've exceeded my fmax by a few MHz. Thank you for your help.

[Kenny_Tan]

Good to hear that the preserve attribute works. For timing improvement, what I would suggest is to look into the training material first. As there are a lot of approaches that can improve your Fmax, and one of it is Design space explorer.

intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

https://www.intel.com/content/altera-www/global/en_us/index/support/training/course/ohdl1130.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1139.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/odswtc02.html

[Kenny_Tan]

Firstly, you need to check what are the source of your RTL? Is your source is verilog, VHDL, AHDL or schematics?

[MGrab6]

The source is VHDL.

[Kenny_Tan]

My suggestion is that you start learning the coding in here https://www.intel.com/content/www/us/en/programmable/support/training/course/ohdl1110.html

After understanding how the vhdl code, you should be able to understand and write the coding in the way to limit the fan out. You can also cross probe the rtl viewer to look into the design where does the code refer to. This will speed your way on the coding side but you first need to understand how VHDL to be written.

[MGrab6]

That was the one little piece of information I was asking for originally. I added 2 separate signals to the vhdl after the initial prescaling counter :Mclk1 <= div_count[1]Mclk2 <= div_count[1]They are defined in the assignment editor to global clocks and are used in other processes.  I think there is a do not optimize option as well but they still get optimized away. Is there an vhdl command in quartus that works something like "asm" in C?I'd edit them directly in the net list with a text editor or rtl viewer but I keep getting thwarted by the software. I'll have a look at the course. Thanks.  null

[Kenny_Tan]

We do not recommend that you edit the netlist or in the rtl viewer. The reason is

1) the project might be use by some other people and it would be really hard to debug when passing down.

2) doing it might cause large computer ram to be used

3) it will not be consistent.

if you have code that had been optimized away, you can right click the vhdl files -> insert template -> vhdl -> synthesis attributes.

Look for the attribute to preserve your code. After preserve your code, run the compilation again and see how the rtl viewer looks like. Most of the time, the code was optimized away due to dangling or connected to gnd.