How to rectify modelsim error "failed to open top_core.vo"?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

How to rectify modelsim error "failed to open top_core.vo"?

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[h=2]I was trying to simulate PCI Express reference design as per instructions given in "ip compiler for pci express (https://www.google.co.in/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=0cb4qfjaaahukewi308hcypphahveky4khbzicio&url=https%3a%2f%2fwww.altera.com%2fliterature%2fug%2fug_pci_express.pdf&ei=tt3cvbeggmsiugs8xapqca&usg=afqjcnh70svgqfxfxgufql7dgu2ix29uxa&sig2=jt7ej5ksplgilqimjejsqq&bvm=bv.99556055,d.c2e&cad=rja)" document. Reference design file I downloaded from altera website and copied in the system. When runtb.do file is runned an error message "failed to open top_core.vo" is shown in the screen.

[/h]Attaching snapshot of error message here.

http://www.alteraforum.com/forum/attachment.php?attachmentid=10966&stc=1

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