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How to reduced intradomain skew in Alter FPGA!

Altera_Forum
Honored Contributor I
982 Views

I am implementing my design into Stratix IV with PMA direct mode transceiver. I got following suggestion while analyzing setup violation. 

 

Place source and destination clock on the same global clock resource for the path from ledp_iptop:ledp_i...lam:lam|prevareq to ledp_iptop:ledp_i...cyc[2]~_emulated 

 

 

Could someone please tell me how to do it? Thanks very much for the help!
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2 Replies
Altera_Forum
Honored Contributor I
101 Views

Hi superjoe, 

Did you solve this issue?
Altera_Forum
Honored Contributor I
101 Views

Create a Global Signal assignment in the Assignment editor and set the value for the assignment to Global.

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