Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
19493 Discussions

How to set clock crossings correctly

Altera_Forum
Honored Contributor II
1,491 Views

I was wondering the best way to do these clock crossings. I have a map_cdc module that is used for clock crossing, and is instantiated in multiple places for different clock domain crossings. I has a .qip file and inside that I have a .sdc which sets these constraints: 

 

set_min_delay -from [get_registers {*|map_cdc:*|PulseSync:in_clock_sync|In_to_Out_Val}] -to [get_registers {*|map_cdc:*|PulseSync:*|In_to_Out_Val_r[0]}] -100 

set_max_delay -from [get_registers {*|map_cdc:*|PulseSync:in_clock_sync|In_to_Out_Val}] -to [get_registers {*|map_cdc:*|PulseSync:*|In_to_Out_Val_r[0]}] 100 

set_max_skew -from [get_registers {*|map_cdc:*|PulseSync:in_clock_sync|In_to_Out_Val}] -to [get_registers {*|map_cdc:*|PulseSync:*|In_to_Out_Val_r[0]}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.8 

set_net_delay -from [get_registers {*|map_cdc:*|PulseSync:in_clock_sync|In_to_Out_Val}] -to [get_registers {*|map_cdc:*|PulseSync:*|In_to_Out_Val_r[0]}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 1 

 

The problem is when I instantiate it multiple times, the constraints overwrite each other (since I have wildcards), which is a problem since I get get values from src_clock_period/dst_clock_period.  

 

In the "SCFIFO and DCFIFO IP Cores User Guide" it shows using the variable $hier_path in order to get the full path to keepers to apply timing constraints to. I was thinking this is what I should use in my constraints so that each time the .qip file is included I can make the .sdc file only apply to that instance (with something like [get_keepers $hier_path|map_cdc:..).) But when I try use this in my sdc files I get the error "hier_path no such variable". 

 

 

Do I need to set this variable somewhere in the .qip file? I can't find any information on it. Or does someone have a better solution? I feel like this should be a common problem.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
164 Views

I have the same problem. I am wondering how to set the $hier_path variable which is mentioned in the DCFIFO user guide.

Altera_Forum
Honored Contributor II
164 Views

What about something like this to get the hierarchy?: 

 

set inst # set inst_list set inst_list {} foreach_in_collection c $inst { lappend inst_list } set hierarchy_list {} # find all hierarchies foreach each_inst $inst_list { # extract the hierarchy regexp {^(.*)\|*$} $each_inst matched hier_path if {$hier_path ni $hierarchy_list} { lappend hierarchy_list $hier_path } } foreach each_inst $hierarchy_list { set_max_skew ... set_min_delay ... set_max_delay ... set_net_delay ... }
XleraSolutions
Beginner
24 Views

Old post, but I came across it recently looking for the same info. The DCFIFO sdc file shows a full usage, including setting that $hier_path variable. 

 

Here is a link to a public version on github... https://github.com/OFS/opae-sdk/blob/master/platforms/platform_if/rtl/platform_shims/utils/quartus_i...

 

Reply