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Novice
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How to set timing constraint to uart

uart is  used as interface of external device. And this device has it's owner clock. When doing timing constraint, should I set uart rxd and txd as false path? or setting timing constraint using virtual clock? or  just set max delay?

 

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7 Replies
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Hi,


You may constrain the I/O signal max and min delay with reference to the virtual clock and any timing exceptions if applicable. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbo... (Page 9 I/O Constraints)


Thanks

Best regards,

KhaiY


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Novice
59 Views

as there is no directly between FPGA clock and external device clock, how do you define the max or min limit?

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Hi,


Do you mean there is no direct relationship between the FPGA clock and external clock? Could you elaborate?


Thanks

Best regards,

KhaiY


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Novice
50 Views

Yes. They are two individual device using uart to communicate. 

FPGA ------uart---------external device(wifi module).

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Novice
49 Views

1. FPGA has its own clock

2. Wifi module has its own clock

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Highlighted
35 Views

Hi,


If they are asynchronous, you may set false path or set multicycle if they are synchronous.


Thanks

Best regards,

KhaiY


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Highlighted
21 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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