How to setup 4ch 25g ethernet in one bank in stratix 10 L-tile?

[PHuan25]

I had setup 2ch 25g ethernet in one bank in stratix 10 successfully. But when I want to setup 4ch, it always recognized 2ch only.

I follow the spec. to config two ATX PLL ip for Main and Clock Buffer. The compilation is passed. But I always only can access the 2ch on Main PLL, the other 2ch on Clock Buffer PLL can not access.

[Deshi_Intel]

Hi Phuan25,

You can generate 25G 4 channels example design directly from 25G IP GUI. Refer to attachment.

From the example design, you can see 25G IP is using 2 ATX PLL to clock 4 25G channels. (one ATX PLL to clock 2 25G channels each)

Thanks.

Regards,

dlim

[PHuan32]

Dear dlim,

Thanks! I had solved the issue. The root cause is setting the same parameters of these two PLLs.

Regards,

Phuan25

[Deshi_Intel]

HI PHuan32,

It's good to know issue is resolved at your side.

Regards,

dlim