I m trying to do the design specified in the video tutorial(link above).
And i managed to connect all blocks without error. but while generating hdl it showing error like:
ERRor: avalon_st_adapter.data format adapter 0: The output interface has no empty signal, but this adapter has been configured to adapt a narrow input interface symbols per beat(1) to a wide output interface symbols per beat(3).
Pls help me to solve this error. i a mtech student. Thanks in advance.
error and design screenshots attached .
Thanks for the quick reply.
My project file attached in the link.
Sir i cleared the errors while generating the HDL bu changing data bits per symbol and plane. I don't know whether it will work on the DE-2 board.
I m doing this for my set project.(I m from VIT vellore,Mtech VLSI Design).
Our project is face recognition. We are using two algorithms in this project. One is face detection algorithm- Viola Jones and second one is face recognition algorithm -Principal component analysis.
I don't how to implement these algorithms in FPGA. We have no option to use NIOS. Can you please help me to how it can be done?
We are confused to how to insert this implemented algorithms into this design.
We are just beginners. We are using verilog HDL
Good to know that you have solved the issue.
Regarding inserting the implementation the face detection & recognition algorithm.
Between dual clock buffer/farmer-buffer/memory and VGA driver.
I have one more doubt in this video processing video tutorial by intel fpga.
How to do the pin assignment for EP4CE115F29C7.
Which all pins of camera should be assigned and whats the corresponding wire pins?
for clock which variable in the code should be assigned?
And for vga which all variable should assigned?
Please guide me.
Thanks in advance
Refer DE2 -115 user manual for all pin details table 4-16 for VGA and table 4-5 clock.
Better download CD ROM from below link