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I/O Bank choice for 64 bit wide EMIF on Cyclone 10 (GX)

KeeganJ
Novice
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I'm having trouble determining what is the optimal pin assignment for a 64-bit wide EMIF interface at 933 MHz. I'm using the 780-pin device.

I know the EMIF will require 3 banks, all in one I/O column, and the address/control bank needs to be the middle of the three banks selected. -- page 124 of document EMIF 683663

 

So my options are:

- Option One: 2A (data), 2J (addr/command), 2K (data)

- Option Two: 2J (data), 2K (addr/command), 2L (data)

 

However I know of a few restrictions:

- If using bank 2A the I/O voltages have to be compatible with the configuration voltage. So this means I would have to power the configuration bank 2A at 1.5V. Unfortunately I can not find any documentation on whether this is legal, and every design example I have seen has shown configuration at 1.8V.

- OCT can't be used in 2L (3V I/O bank) which would result in a "lower frequency restriction" -- not explained, but mentioned on page 123 of EMIF document 683663. Presumably I can not tolerate "frequency restrictions" if the RAM is to operate at the highest supported speed. Also, there is a workaround described, but it shows address/command in bank 2L, which would be not compatible with the 64-bit wide interface, since that does not place the address/command bank in the middle.

 

So for now I'm just assuming I can go with Option One, and power bank 2A at 1.5V, and still configure the device successfully. Is this allowed? The MT25Q flash SPI chips are 1.8V supply, but I know the I/Os can tolerate 1.8V even if powered with 1.5V, so it may simply require a level shifter.

 

Can you help determine the optimal pin and bank assignment?

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AdzimZM_Intel
Employee
202 Views

Hi KeeganJ,


Thank you for submitting you question in Intel Community,

I'm Adzim, application engineer will assist you in this thread.


You have right understanding on IO banks usage.

I also would like to suggest to use "Option One" because you can use termination on LVDS IO bank.

The VCCIO for DDR3 protocol must be driven at 1.5V.

You need to make sure the voltage is correct for every IO banks that have been used for EMIF IP.


The option below is correct.

- Option One: 2A (data), 2J (addr/command), 2K (data)


Regards,

Adzim



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2 Replies
AdzimZM_Intel
Employee
203 Views

Hi KeeganJ,


Thank you for submitting you question in Intel Community,

I'm Adzim, application engineer will assist you in this thread.


You have right understanding on IO banks usage.

I also would like to suggest to use "Option One" because you can use termination on LVDS IO bank.

The VCCIO for DDR3 protocol must be driven at 1.5V.

You need to make sure the voltage is correct for every IO banks that have been used for EMIF IP.


The option below is correct.

- Option One: 2A (data), 2J (addr/command), 2K (data)


Regards,

Adzim



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AdzimZM_Intel
Employee
188 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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