I/O Standard in Pin planner of Intel Quartus prime

[fpga_enthusiastic]

Hello all,

Is it possible to change I/O standard in Pin planner other than the given options. For ex. 3.3 V LVTTL is there in given options but I need to change it as 3.5V but in given I/O standard 3.5V option is not present. How to change that?

Please guide

[FvM]

Hi,
you can refer to device datasheet to learn about supported IO standards. No recent FPGA family supports higher nominal IO supply voltage than 3.3V (+/- 5 % tolerance).

It will be typically no problem to connect peripherals using non-standard 3.5V logic supply, you should worry however about possible overshoot that might exceed absolute maximum input voltage of 4.2V. 

[fpga_enthusiastic]

Thank You. But how can we give pin input setting to 3.5V LVTTL or 3.8V  LVTTL and generate a power report. Is it possible? Because we need to check how it will affect instead of 3.3v  LVTTL to 3.5 OR 3.8V  LVTTL and need to check the power report and need to check behavior in simulation 

[Nurina]

Hi,

Does above reply help with your problem?

Regards,

Nurina

[Nurina]

Hi,

We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If any answer from the community or Intel Support are helpful, feel free to rank your support experience by rating 4/5 survey. Please let me know of any inconvenience so that I may improve your future service experience.

Best regards,

Nurina

[FvM]

Hi,
I fear you don't yet understand the concept of defined IO standards.

The behaviour beyond specified VCCIO and logic voltages is simply undefined. You can't set IO standards with higher logic voltage than LVTTL/CMOS 3.3V and you shouldn't expect data or simulation support for it.

Does your intended device operation respect specified VCCIO voltage range and maximal ratings for input voltage? If not, you seem to look for trouble.

Input characteristics for extended voltage range are detailed described in IBIS files.