recently while working on a design with EP4CE30F29I8LN where all our I/O banks were powered to 3.3V and under device and pin options I had selected 3.3-V LVCMOS. However one of the I/O lines had to be adjusted for increased current strength from default 2 mA and also the slew rate. The only way I could do it was to change the I/O standard of one entire bank to 3.0-V LVCMOS and this made it work. Is this okay even though I externally connect to 3.3V?
I see you are using Cyclone IV on your design. Are you referring to Vccio? If yes, the range of Vccio in 3.0-V LVCMOS is from 2.85V to 3.15V. Supplying Vccio of 3.3V on this bank is not recommended since it is above the range and I cannot validate whether it will be safe or not to your device. I would recommend you to follow I/O Standard Specs from Cyclone IV Device Datasheet Table 1-15 page 12: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pd... .
Unfortunately no. The current strength from the table I shared with you is only from -2mA to 2mA for 3.3V LVCMOS. I am sorry I cannot validate if it will be safe for your device if you set specifications beyond our range from that document. Do you need any more clarification?