I Reconfig Clock FPGA - Intel Community

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I Reconfig Clock FPGA

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I am in the early stages of designing a 100 Gb F tile.

Can i reconfig clock come from a pll or does it have to be its own dedicated clock from the fabric?

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Hi,

Can you please clarify which clock signal are you talking about in the diagram? The Reference clk(s) at the bottom? Or the i_clk_rx and i_clk_tx ?

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Hi,

Any comment on my previous query?

Regards

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