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I'm not sure what you're asking. Can you post the code? Any top-level ports would appear in the Pin Planner for assignment after performing at least Analysis & Elaboration or full synthesis on the design.
#iwork4intel
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Hi,
Yes, In addition, refer the below link after full synthesis,
https://www.youtube.com/watch?v=Jn5keRQAuyw
I would suggest go through the Intel free online training since you are newbie to FPGA,
https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html
Regards,
Vicky

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