I am currently using a Altera FPGA (EP3C16F484C8N). I need to provide 1.2V to the VCCD_PLL and VCCINT pins. I would like to know the acceptable noise level (Vrms) to those pins.

[MGane2]

Based on the Noise level of those pins (VCCD_PLL & VCCINT) I need to qualify the LDOs. In general, the LDO's have output noise voltage of 10 to 100 uVrms. I would like to know what is the specified / recommended acceptance level.

[Rahul_S_Intel1]

Hi ,

As of now, Intel does not provide the nose level for VCCD_PLL and VCCINT , decoupling have to provided depends up on decoupling requirements.

Regards,

RS

[JScho6]

Can't directly comment on the specific part you're using, but I have experience with the EP3C25 in EQFP144, and with the 10CL025 in 256-ball fineline BGA, which is *very* similar.

Despite low-noise LDOs in the design and extra ferrite/ceramic cap filtering for the PLL voltages, we did have trouble with the PLLs for a fairly low-frequency source clock of 8MHz. We've had frequent loss of lock despite lots of added filtering.

The ultimate solution was to add an extra 3.3V oscillator with a fixed frequency of 50MHz. The PLL is a lot happier with that, does not lose lock even with the worst noise we can add on the source voltage here in the lab.

So I guess that the acceptable noise greatly depends on the source clock, and is therefore a lot more complicated to specify than you may think at first sight.

greetings from Germany,

Jens