Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
19508 Discussions

I am trying to find a clear info. regarding this part EP3SL110F1152C2N 1- the maximum number of single-ended digital input/outputs. 2. the aggregate one-way peak serial transceiver data rate.

oElmo1
Beginner
374 Views
 
0 Kudos
2 Replies
CheePin_C_Intel
Employee
108 Views
Hi, As I understand it, you have some inquiries related to the number of IOs supported in your targeted SIII device. For your information, you may refer to the "Table 1–2. Package Options and I/O Pin Counts" in the Stratix III Device Family Overview document (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stx3/stx3_siii51001.pdf) for further details. From the table, it is showing 744 max IO pin count for your targeted device. Regarding your inquiry on the transceiver, for your information, transceiver is not available in SIII device. Sorry for the inconvenience. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
CheePin_C_Intel
Employee
108 Views
Hi, As I understand it, it has been some time since I last heard from you. I would set this case to closed at this moment. Feel free to file a new case if you have any further question related to this request. Thank you for your understanding. Best regards, Chee Pin
Reply