I can't work with Toolkit

[AvramG]

I compiled the attached project (exo_r_c10gx_forum.7z) with 10G PHY/MAC and DDR3 controller.

I use the Quartus Prime Version 21.3.0 Build 170 09/23/2021 SC Pro Edition.

I want to run the toolkit on our new boards with Cyclone 10 - 10cx105yu484i6g.

Unfortunately, when I open the toolkit, I don't see any instances.

I took the PHY/MAC codes from the PHY's example design (altera_eth_10g_mac_base_r_wrap as a black box).

I have 3 JTAG components:

1. altera_emif_c10 (add EMIF debug interface for debug toolkit)

2. altera_jtag_avalon_master

3.  altera_xcvr_native_a10 - 10G transceiver (enable native PHY debug master endpoint)

I can see them in the TCL console:
% lindex [ get_service_paths master ] 0
/devices/10CX105Y@1#USB-1/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_1/phy_0/emif_c10_0_col_if_colmaster.master
% lindex [ get_service_paths master ] 1
/devices/10CX105Y@1#USB-1/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_2/phy_1/master_0.master
% lindex [ get_service_paths master ] 2
/devices/10CX105Y@1#USB-1/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_3/alt_sld_fab_0_alt_sld_fab_0_host_link_jtag.h2t/alt_sld_fab_0_alt_sld_fab_0_stfabric.h2t_0/alt_sld_fab_0_alt_sld_fab_0_memfabric_transacto.avalon_master
%

 I write/read the registers in the bank_registers.vhd by I2C commands.  

See the attached registers.jpg image.

I checked the DDR with our ddr3_dvt_avl checker (register 0xc in the bank_register) and the results are O.K

I also checked the clocks (registers 0x4)... O.K

I have 2 signal tap files: with mac_csr signals and without mac_csr signals.

When I compile without the mac_csr signals, the TCL console could identify the 3 jtag components and the signal tap is ready for use.

When I compile with the mac_csr signals, the TCL console couldn't identify the 3 jtag components and the signal tap is not working ("Program the device to continue").

Also (without mac_csr) in the External Memory Interface Toolkit I get the error:

Could not create process for System Console using command c:/intelfpga_pro/21.3/quartus/sopc_builder/bin/system-console.exe --server. Ensure that System Console is correctly installed.

I reinstall the Quartus software...it didn't help.

Last question,  I want to control the PHY/MAC registers with the JTAG to Avalon Master Bridge.

I connected the JTAG to Avalon Master Bridge in the jtag_avmm.qsys to Avalon Memory Mapped Pipeline Bridge.

I don't know how could I connect the mm_bridge_mac_readdatavalid from Avalon Memory Mapped Pipeline Bridge, when the PHY/MAC CSR don't have this signal.

Summary of the problems:

1. I don't see any instances in the toolkit

2. Why signal tap with mac_csr is not working?

3. Why I haven't the system-console.exe file for the Memory toolkit?

4. How could I connect the mm_bridge_mac_readdatavalid  signal?

Thanks,

Avram

[AdzimZM_Intel]

Hi Avram,

Thank you for using Intel Community.

I'm Adzim will assist you in this issue.

The problem that you're facing is a known issue which can be found in the KDB article: https://www.intel.com/content/www/us/en/support/programmable/articles/000090139.html

I have checked that the issue has been fixed in latest Quartus version.

For Quartus version 21.3, a patch will be available and currently it's still under the testing.

Regards,

Adzim

[AdzimZM_Intel]

Hi Avram,

Do you have any further question in this topic?

Regards,

Adzim

[AvramG]

Sorry,

I didn't notice that your answers sent to my "Junk Email".

Thanks for your answers.

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.