Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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I cannot update the PLL output clock Frequency

PGigl
Partner
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I have enable all macros as instructed.  I still cannot update the clock frequency.  It states that the page is protected and to unprotect I will need a password?

 

I am using Microsoft 365 and again, I have gone into the trust center and enabled all macros​

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SreekumarR_G_Intel
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i am not sure i follow you , can you please explain me in detail ; such as which device , quartus version etc ;

would it possible to attach the design so that i can have a look ?

 

Thank you ,

 

Regards,

Sree

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