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I have a customer who is looking to use the PLL in the MAX 10 to take a 25 MHz clock and generate a 100 MHz clock for a PCIe interface. Will the PLL in the MAX 10 meet the jitter requirements of PCIe Gen1?

SZack
Partner
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JonWay_C_Intel
Employee
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Hi @SZack​ The PCIe refclk requirement is 100Mhz +/- 300ppm. So if you make a conversion to ps for easy comparison (https://www.jitterlabs.com/support/calculators/ppm) to the jitter spec in the MAX10 datasheet (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf Table 27), you will find that the PLL output clock WILL NOT meet the PCIe refclk requirement.

 

I hope this answers your questions.

SZack
Partner
138 Views

Thanks Jw.

I did come to the same conclusion after finding the jitterlabs site you mentioned. What puzzled me is that the jitter requirement of 6ps is so stringent that several PCIe clock generators I looked at do not meet this spec so I wasn't sure if this calculation was relevant. And when I looked at some documents describing the maximum phase noise and jitter requirements for PCIe Gen1 I saw numbers in the 85ps range. I also read that many PCIe applications use spread spectrum clocking and the MAX 10 PLL can definitely NOT provide that kind of clock output.

 

Given my lack of certainty about exactly what the specs meant I recommended that the customer use a dedicated clock generator.

 

Steve

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