I have a design code wrote in VHDL. I'm planning to test the code using system verilog i.e to debug the code,to perform coverage analysis,functional coverage etc.which tool support this kind of testing?

[mmn001]

I'm a beginner of system verilog programming, i want to do verification of vhdl codes using system verilog but very much confused with which tool to use,how to use.need some guidelines..please help

[Vicky1]

Hi,

You can use Questasim for verification purpose, which allows you to check coverage analysis. you can also check the EDA Playground.

There are few websites/Forums which will help to you for verification like,

http://www.testbench.in/

https://www.verificationguide.com/p/home.html

https://verificationacademy.com/

https://www.chipverify.com/

Please help me to close this case.

Regards,

Vicky