I need to generate a stream of serial binary data from a clock source. In other words, the generated serial binary data must have the same frequency than the clock source. Then, I need to save it in a memory at the same speed. (All inside the FPGA)
Well, I need the maximum frequency as posible. My questions are:
Thank you, I hope you can understand me. Sorry for my english. I only need some idea, I don't need an exhaustive guide. 😀
You don't say what FPGA family you're looking to use, but you won't get anywhere near 2GHz just using logic to generate your serial stream, in any family. Cyclone 10 may allow you to serialise data @ 500MHz, but no more.
You'll have to look at using a transceiver block of IP to serialise and deserialise your data. Look at the Transceiver 'PHY User Guide'. That will allow you to serialise and deserialise data up to and over 6Gbps.