Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
1,084 Views

IIR filter implementation on cyclone FPGA

Hello everyone, 

 

i am trying to design a second order LPF with 8Hz cutoff frequency and sampling frequency 20kHz, below is the z transform 

 

y(z)/x(z) = 0.1576*10^(-5)*(1 +2*z^(-1) + z^(-2))/(1 -1.9964z^(-1) + .9965z^(-2)) 

 

i have used matlab to generate this function. can anybody tell me how to implement this function on FPGA. thanks in advace
0 Kudos
5 Replies
Highlighted
Valued Contributor III
18 Views

Re: IIR filter implementation on cyclone FPGA

refer to page 7-37 of this doc: 

 

http://www.altera.com/literature/hb/stx/ch_7_vol_2.pdf
0 Kudos
Highlighted
Valued Contributor III
18 Views

Re: IIR filter implementation on cyclone FPGA

Hi kaz 

 

thanks for reply,  

i have to write a code in verilog HDL for above filter, my input and output bit width is 12bit and its vary from -10V to 10V so the precision will be around 5mV per bit. can you please help me in this.
0 Kudos
Highlighted
Valued Contributor III
18 Views

Re: IIR filter implementation on cyclone FPGA

have you taken a look at a couple of the design examples? 

 

http://www.altera.com/support/examples/verilog/ver_base_iir.html
0 Kudos
Highlighted
Valued Contributor III
18 Views

Re: IIR filter implementation on cyclone FPGA

that example not helping me out, if some one has source code in verilog for above filter thn plz help me...

0 Kudos
Highlighted
Valued Contributor III
18 Views

Re: IIR filter implementation on cyclone FPGA

the verilog code that I have written for the above filter:- 

 

equation tht I have implemented- 

w[n] = a[0]*w[n-1] + a[1]*w[n-2] + a[2]*x[n] + a[3]*x[n-1] + a[4]*x[n-2]; 

y[n] = b*w[n]; 

 

// a[0] = 1.9964*2^10, a[1] = .9965*2^10; a[2] =a[4] =.1576*1024 = 1/2*a[3], b = 10^(-5)*2^21; 

 

below is the code:- 

module buttersos1(clk,X,Y); 

input clk; // frequency 20kHz 

input signed [11:0]X; //input  

output signed [11:0] Y; //output 

reg signed [23:0]x1,x2,w1,w2; 

reg signed [35:0] temp,temp1; 

reg signed [11:0] a[4:0]; 

initial begin  

b[0] = 2044; b[1] = -1020; b[2] = 161; b[3] = 322; b[4] = 161; 

x1 = 0;x2 = 0; w1 = 0; w2 = 0;w = 0; 

end 

always @(posedge clk) begin 

temp = b[0]*w1 + b[1]*w2 + b[2]*X + b[3]*x1 + b[4]*x2; 

w2 = w1; 

w1 = temp[33:10]; // scaled by 2^10 ,so leaving last 10 bit 

x2 = x1; 

x1 = X; 

temp1 = 21*w1; 

end 

 

assign W = temp1[32:21]; //saled by 2^21, so leaving last 21 bit 

endmodule 

 

can anybody tell me wat is the problem with above program... 

I have used same algorithm to program my other filter and that is workng well.
0 Kudos