During FPGA reconfiguration what is the status of FPGA I/O pins. Will the I/Os toggle or retain the state driven by the previous image.
How the I/O transition takes place during reconfiguration.
For your questions it will depends on your IO configurations that you set. You may refer to this document for more details: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf
I hope this helps.