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Altera_Forum
Honored Contributor I
737 Views

IOBuff Usage

Hi, 

 

I have input to output direct mapping in my design. I am not able to time close it to 5ns because of IC Delay. 

 

input is in 3.3 V domain: 

set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to unc_jtag_tck  

 

output in 1.8V domain: 

set_instance_assignment -name IO_STANDARD "1.8-V" -to tck_unc2 

 

logic: 

assign tck_unc2 = unc_jtag_tck; 

 

constraint given is: 

 

set_max_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc2}] 1.000 

set_min_delay -from [get_ports {unc_jtag_tck}] -to [get_ports {tck_unc2}] 0.500 

 

 

timequest is showing 10.25 ns data delay for this path!!! 

 

Is it possible make the ports as IOBuff?? 

Is there any other way to time close this logic path? 

 

 

 

Thanks, 

Neeraj
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5 Replies
Altera_Forum
Honored Contributor I
9 Views

There's no logic between the input and the output? Strange. 

 

I'd check the Chip Planner and the Fitter Information tab in a detailed timing report to try to figure out why the Fitter routed this path so poorly. There must be some physical placement requirement that is causing the delay. 

 

Also, how full is your device?
Altera_Forum
Honored Contributor I
9 Views

Hi sstrell, 

 

Actually I removed a mux in the path to get the best result(still I cant time close the design!). 

Pin placement is on the diagonal ends of the device(B18 and R1 for example) and it cannot be changed as board is already designed. 

My device is just 10% full. Device is Cyclone IV E - EP4CE55F23C8. I am surprised to see the pin to pin delay of ~10.5 ns. 

 

Am I missing any techniques to time close this particular path? 

 

Thanks, 

Neeraj
Altera_Forum
Honored Contributor I
9 Views

Where are the delays? Again, did you check the Chip Planner or Extra Fitter Info tabs to see what physical constraints are leading to such a large delay? In your detailed timing report, where are the largest incremental delays (reported on the Data Path tab)? 

 

Posting screenshots of your timing report(s) may help.
Altera_Forum
Honored Contributor I
9 Views

Hi, 

 

Screenshot of chip planner view and path delay report is attached here. 

 

 

 

Thanks, 

Neeraj
Altera_Forum
Honored Contributor I
9 Views

Wow, that is a huge incremental delay in the output I/O buffer. Does that pin have some other function attached to it or some other assignment you've created to account for that delay? Do you see an over 6 ns delay on other outputs in your design? Do you have any set_output_delay constraints in your .sdc file (which you should)?

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