Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20245 Discussions

IP for FPLL Cyclone 10 GX

jmenn
Beginner
553 Views

How to instantiate FPLL of cyclone 10 GX device. I don't see this in the PLL IP list. According device overview datasheet 10CX105 there are 6 IOPLL.

According the compilation report there are only 4 IOPLL but 8 FPLL

 

Regards, Jan

 

0 Kudos
1 Solution
SreekumarR_G_Intel
359 Views

Hello Jan,

Can you check the 20.1 pro ?

 

Thank you ?

 

Regards,

Sree

View solution in original post

0 Kudos
5 Replies
SreekumarR_G_Intel
360 Views

Hello Jan ,

i am bit confused on your requirement , As of I now i understood cyclone 10 GX FPLL used as the XCVR (Transceiver) PLL whereas IOPLL's are used for the FPGA fabric.

About the count difference would it possible to share the screen shot of Compliation report and Datasheet referennce number where it mentioned as 6.

 

Thank you ,

 

Regards,

Sree

0 Kudos
jmenn
Beginner
359 Views

Hello Snee

I find out that the number of PLL depends on the number of banks cq device pin count

484 pins device has 4 IOPLL (4 banks) 672 pins has 5 IOPLL (banks) and 780 pins has 6 IOPLL (banks).

In the device list however all has 6 see enclosed screenshot and compilation reports.

Also in the documentation i cannot find that number of pll is dependent on package.

 

Regards, Jan

 

 

 

0 Kudos
jmenn
Beginner
359 Views
posted a file.
0 Kudos
SreekumarR_G_Intel
359 Views

Hello Jan,

Hope you safe there,

Just would like to let you know i raised the concern to the internal team . will let you know as soon i get the update.

 

Thanks

Sree

0 Kudos
SreekumarR_G_Intel
360 Views

Hello Jan,

Can you check the 20.1 pro ?

 

Thank you ?

 

Regards,

Sree

0 Kudos
Reply