Implementation a common tristate output for a tristate array

[Altera_Forum]

Hello everybody. 

I am working on a EPF10k20RC240-4 FPGA. I have a few outputs with enables. these output connect together in a connecting point. Now I want to get my favourite output by selecting it via setting the enable. How can get it?  In the oder word, I want to have a tristate ('0','1','z') array with one common output. The common output value show the value of the selected output via it's enable. All the best Bahman.

[Altera_Forum]

do you have any code yet? and what language are you trying to use?

[Altera_Forum]

--- Quote Start ---  do you have any code yet? and what language are you trying to use?  --- Quote End ---     Hello. I have some code about it in VHDL,but I am not sure of it. the code is following. Do you have a better code than mine? Thanks alot. ---------------------------- library ieee; use ieee.std_logic_1164.all; entity tristate_dr is port( d_in: in std_logic_vector(7 downto 0);  en: in std_logic;  d_out:out std_logic_vector(7 downto 0)  );  end tristate_dr;  architecture behavior of tristate_dr is begin  process(d_in, en)  begin  if en='1' then  d_out <= d_in;  else   d_out <= "ZZZZZZZZ";  end if;  end process; end behavior;

[Altera_Forum]

Hi, 

do you have one external output (a pin) for all output signals or do you have one output pin for each output and connect them together outside of your device ? If you want to connect the outputs together internally (and route them to one output pin) you should not do this with tri-state signals. You should use a mux instead.