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Implementation of option bits FPGA configurations



I am currently working on a project that involves an Arria II GX FPGA with  Max II CPLD, and CFI_256 Flash memory in FPP X8 mode. I have a requirement of using only  page 0 in the flash memory for configuration purposes.

In this context, I have a few questions regarding the implementation of option bits with this specific configuration:

  1. How can I effectively allocate and utilize option bits within the limited address space of only  pages 0?
  2. Are there any specific considerations or recommendations for mapping and assigning option bits to the available memory addresses in this configuration?
  3. What would be the appropriate approach for storing and accessing the option bits within the flash memory?
  4. Are there any constraints or limitations I should be aware of when implementing option bits with such a restricted address range?
  5. I want to calculate option bit if we have only page 0 my start address is page 0 0x00020000 and end address is 0x00ABFFFF . In convert Programming file  Option/Boot info  I  added 0x00018000 maybe this is wrong confused confused
  6. I also added values 0x00018000 in mega function core parallels flash loader option bit  

I have referred to the documentation and user guides available for the ugl_pfl.pdf, but I would appreciate any additional guidance, insights, or resources that can help me effectively implement option bits in this constrained setup.

Thank you for your time and assistance!

Best regards,


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Hi nome,

You may take a look the table of Option Bits Sector Format and Figure 12 below which can be found from Parallel Flash Loader Intel® FPGA IP User Guide. It might give you some insight.

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