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Altera_Forum
Honored Contributor I
2,556 Views

Implementing CAM (Content Addressable Memory) on Cyclone III

Hi everyone, 

 

I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. 

 

In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CAM (Content Addressable Memory) on a Cyclone-III FPGA. 

 

Can anyone help me with that? 

 

Thanks in advance 

Modellpilot
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23 Replies
Altera_Forum
Honored Contributor I
187 Views

speak out ur deign spec such as 512x32bit,dual port,dual clock. 

In Quartus, it's easy to realize by using megawiard tool!
Altera_Forum
Honored Contributor I
187 Views

Sorry, but I think there is a missunderstanding: I'm looking for a CAM not for a RAM :cool:  

 

I allready had a look on Quartus. And Yes, the MegaWizard Plug-In Manager provides a lot of different memory controllers (single/dual-port, single/dual-clock, RAM/ROM/SREG). But CAMs are only supported when using an APEX device. When selecting a Cyclone-III CAMs and Flash Memory is disabled :mad:  

 

Modellpilot
Altera_Forum
Honored Contributor I
187 Views

What size do you want? What speeds? Is it Ternary(this is often a deal-breaker for larger CAMs, unless you don't mind using a ton of resources). There's a nice trick for making binary CAMs out of RAMs. I have a parameterized VHDL design for it, but I wrote it a few years ago and it targets either M4Ks or M512s. I can modify it for M9Ks, or might post-it as is for now, but am curious what your requirements are, as it might not work for you.

Altera_Forum
Honored Contributor I
187 Views

I need a 24x12 CAM (means 5-bit address and 12-bit word size). It would be great if you could help me with a VHDL code :)  

 

A version for M9Ks would be fine. But I think it is no big deal to adapt an example for M4Ks. Right? Thanks in advance!
Altera_Forum
Honored Contributor I
187 Views

An M9K can do a 32x8 CAM, so you'll basically change the parameters in M9K_CAM.vhd to do a 32x16 CAM(it needs to be a multiple of these dimensions), and then just tie off the extra ports. I built this quickly but believe it is correct. There is a presentation that is very old on this topic(it was done as Stratix was rolling out). I have a document that refers to it, so together you can use them for understanding. (Not the most professional delivery, but hey, if it works.) You can also just use the M9K_CAM.vhd and M9K.vhd files and just play with it yourself.

Altera_Forum
Honored Contributor I
187 Views

Hello,Modellpilot 

I misunderstood u and you can find a 256x8 CAM 

in 

 

http://www.geocities.com/deepakgeorge2000/cam.htm (http://www.geocities.com/deepakgeorge2000/cam.htm

 

with VHDL code.Hope can help you.
Altera_Forum
Honored Contributor I
187 Views

Greetings, 

I have a problem filling the CAM with data ,does anybody know how I can initialize the CAM using the initial file ?or is there any other way ? please help me, 

Many thanks in advance
Altera_Forum
Honored Contributor I
187 Views

Hi mehryar, 

unfortunately I can't help you regarding a question about the models of Rsyc or markman. After all I analyzed the usefull hints and realized a custom CAM implementation which is appropriate to the dedicated requirements of my application. 

Best regards, Modelpilot!
Altera_Forum
Honored Contributor I
187 Views

Hi modelpilot, 

Did you write your own CAM from scratch? or you used the CAM provided from RYSC? either ways can you send me your design ,if it is possible. 

I tried both the fast CAM from altera and parameterized CAM by RYSC but still I don’t know how to initialize it! 

Altera_Forum
Honored Contributor I
187 Views

Hi mehryar, 

yes I wrote my CAM from scratch. Because the application required a very high performance for a dedicated context-specific filtering. Due to the use of this model in one of our products, I can't send you my design. Sorry! 

Modelpilot
Altera_Forum
Honored Contributor I
187 Views

Hi, I have a doubt abou this. This CAM size that a M9K block can implement is number of words X number of bits of each word or it is number of bit address X number of bits of each word? 

Thanks in advance!!!:)
Altera_Forum
Honored Contributor I
187 Views

Neither, at least with the design I posted, it's a 32x8 CAM. Be sure to look at it, since is uses different widths between reads and writes. On the write side, the data AND address are combined into a single write address. This implementation allows the write and read to occur in a single clock cycle. 

It seems like a huge reduction from all the bits in an M9K down to just a 32x8 CAM, but that's because it's just a RAM. A CAM needs to look at all locations for a match, so if you really wanted to store a word at each location, then you would need a state-machine that reads every location and checks for a match, i.e. it would be MANY clock cycles for each read. Some designs can tolerate this, but it quickly becomes unmanagable. The one I posted is very straightforward in implementation(once you understand how it works), but is small. I've seen plenty of cases where users need a much larger CAM and find they're dedicating all of the memory to this function and hence this implementation doesn't work.
Altera_Forum
Honored Contributor I
187 Views

Thanks for the tips!! But I need a CAM with 64 words X 64 bits wide, what do you suggest for implement this kind of CAM? 

Once more, thanks!!:)
Altera_Forum
Honored Contributor I
187 Views

The HDL is parameterized, so just put that in. I believe a 64x64 will require 16 M9Ks(x2 to get the width and x8 to get the depth). That should be do-able.

Altera_Forum
Honored Contributor I
187 Views

Do you have parameterized_cam in Verilog code?

Altera_Forum
Honored Contributor I
187 Views

I have created a Verilog parameterized CAM that you may find useful. I'll attach it here. It is a Quartus II archive file that contains a simulation environment in the sim directory, and some documentation in the doc directory.

Altera_Forum
Honored Contributor I
187 Views

Dear Rysc, 

Can your Parameterized_CAM be configured to  

parameter NUM_WORDS = 4096; 

parameter WRADDR_WIDTH = 12; 

parameter WIDTH = 16; 

or not ?
Altera_Forum
Honored Contributor I
187 Views

What happened when you tried it? If the base M9K makes a 32x8 CAM, then the depth and width look like multiples, so I see no problem. Although I think it's going to take 256 M9Ks to get that, so it will use a lot of resources.

Altera_Forum
Honored Contributor I
187 Views

With FOR loop times from 2048 to 4096, the PC can not synthesize, out of memory in module quartus_map.exe 

May be the numbers of loop is too larger to synthesize
Altera_Forum
Honored Contributor I
68 Views

Hi, 

I am new to this and I have a query. Is this code valid for cyclone 4 too? I am not having altsyncram option in here. I have a M9k block and need a CAM of 128 bytes memory with 8 bits of data and 8 bits of address. 

 

Thanks 

 

 

--- Quote Start ---  

An M9K can do a 32x8 CAM, so you'll basically change the parameters in M9K_CAM.vhd to do a 32x16 CAM(it needs to be a multiple of these dimensions), and then just tie off the extra ports. I built this quickly but believe it is correct. There is a presentation that is very old on this topic(it was done as Stratix was rolling out). I have a document that refers to it, so together you can use them for understanding. (Not the most professional delivery, but hey, if it works.) You can also just use the M9K_CAM.vhd and M9K.vhd files and just play with it yourself. 

--- Quote End ---  

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