Implementing CAM (Content Addressable Memory) on Cyclone III

[Altera_Forum]

Hi everyone, 

 I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs.  In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CAM (Content Addressable Memory) on a Cyclone-III FPGA.  Can anyone help me with that?  Thanks in advance Modellpilot

[Altera_Forum]

It should be RTL that can be synthesized for any family, except for the RAM. To be honest, I think altsyncram should work for Cyclone IV. Have you tried compiling? 

If it errors out, then you would need to remove it and put in your own Cyclone IV RAM, whether it be a MegaFunction or inferring it, whichever you prefer.

[Altera_Forum]

Yes. it compiles by assigning the generics to the values from your code. Still wondering how you came up with these values. And about your code for CAM, the depth is 128 and the data bits is 16. I have just changed the width to 8 to have a 128 bytes of data.  

   --- Quote Start ---  It should be RTL that can be synthesized for any family, except for the RAM. To be honest, I think altsyncram should work for Cyclone IV. Have you tried compiling? If it errors out, then you would need to remove it and put in your own Cyclone IV RAM, whether it be a MegaFunction or inferring it, whichever you prefer.  --- Quote End ---  

[Altera_Forum]

Hello Again, 

  Is it possible to erase the used CAM completely for re-use?