Improve timing using multiple PLL

[Altera_Forum]

Hello all, 

 In device like Cyclone V A9 there are 8 PLL. Generally I generate system clock from one PLL in normal mode but there is a way to improve timings using nearer PLL for some design parts using same system clock?  Thank you

[Altera_Forum]

I can better compensate remote locations with another PLL in sync with system clock?

[Altera_Forum]

Usually clock tree is global and if an improvement occurs due to multiple PLLs then it is likely a matter of chance fitting.

[Altera_Forum]

So just one PLL at time can be used and fitter chose the best?