In Figure 5 of the Stratix 10 Clocking and PLL Architecture document (see below) I wanted to know how to enable the I/O PLL Clock Gates shown in the block on the left. I thought the Distributed Sector Level setting controlled the clock gates in the SCLK block on the right. Figure 5 shows three different clock gates (I/O PLL Clock Gates, Root Clock Gate, Clock Gate in the SCLK section) but I only see two choices in the Clock Control IP.
Ah ha...i see what you mean.
You are right! you can gate each of the output clock individually by setting the mgmt_address[9:8] to 2'b10, and depending on which output to gate/ungate, you have to set the mgmt_writedata[7:0] accordingly.
You can refer to the example design and description from below: