In the Stratix 10 Clocking User Guide (Dec 2018) section 2.1.4.1.3 on page 11 describes a way to get the clocks coming out of the I/O PLL. But I don't see how I enable this functionality in the I/O PLL parameter editor. How do I turn on this feature?

[JonWay_C_Intel]

Hi @SZack​ 

It is not in the PLL IP, instead it is in the Clock Control IP --> Clock Enable Type --> Distributed

[SZack]

In Figure 5 of the Stratix 10 Clocking and PLL Architecture document (see below) I wanted to know how to enable the I/O PLL Clock Gates shown in the block on the left. I thought the Distributed Sector Level setting controlled the clock gates in the SCLK block on the right. Figure 5 shows three different clock gates (I/O PLL Clock Gates, Root Clock Gate, Clock Gate in the SCLK section) but I only see two choices in the Clock Control IP.

[JonWay_C_Intel]

Ah ha...i see what you mean.

You are right! you can gate each of the output clock individually by setting the mgmt_address[9:8] to 2'b10, and depending on which output to gate/ungate, you have to set the mgmt_writedata[7:0] accordingly.

You can refer to the example design and description from below:

https://www.intel.com/content/www/us/en/programmable/documentation/mcn1440569668630.html#xxd1489118045253