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Inconsistent resources usage result from P4-14 program and P4-16 program

Xiangyu95
Beginner
296 Views

I have one question about the resources usage from Tofino compiler. Since I create two programs written in P4-16 and P4-14 (shown below) with the same semantics (Two tables with Action dependency), but the Tofino compiler allocates two stages for P4-14 benchmark but only one stage for P4-16 benchmark. We only need to focus on the Ingress part of these two programs but ignore other architecture parts. In addition, I am also not sure the right place to see ALU's operation details in Tofino switch. Can anyone help me figure out these issues?

In addition, I am not sure whether this is the suitable place to post this question because of the change from Barefoot platform to Intel platform. If anyone has some suggestions about a better place to post, I will really appreciate that. We can also sync up offline if you need more details (email me at xg673@nyu.edu) 

Thanks a lot for any possible help in advance.

 

--------------------------------P4-16 program:--------------------------------

#include <core.p4>
#define __TARGET_TOFINO__ 1
#include <tna.p4>

/* Declare Header */
header ethernet_t {
bit<48> dstAddr;
bit<48> srcAddr;
bit<16> etherType;
}

struct Headers {
ethernet_t ethernet;
}

header standard_metadata_t {
bit<9> ingress_port;
bit<9> egress_spec;
bit<9> egress_port;
bit<32> instance_type;
bit<32> packet_length;
//
// @ALias is used to generate the field_alias section of the BMV2 JSON.
// Field alias creates a mapping from the metadata name in P4 program to
// the behavioral model's internal metadata name. Here we use it to
// expose all metadata supported by simple switch to the user through
// standard_metadata_t.
//
// flattening fields that exist in bmv2-ss
// queueing metadata
@ALias("queueing_metadata.enq_timestamp")
bit<32> enq_timestamp;
@ALias("queueing_metadata.enq_qdepth")
bit<19> enq_qdepth;
@ALias("queueing_metadata.deq_timedelta")
bit<32> deq_timedelta;
/// queue depth at the packet dequeue time.
@ALias("queueing_metadata.deq_qdepth")
bit<19> deq_qdepth;
// intrinsic metadata
@ALias("intrinsic_metadata.ingress_global_timestamp")
bit<48> ingress_global_timestamp;
@ALias("intrinsic_metadata.egress_global_timestamp")
bit<48> egress_global_timestamp;
/// multicast group id (key for the mcast replication table)
@ALias("intrinsic_metadata.mcast_grp")
bit<16> mcast_grp;
/// Replication ID for multicast
@ALias("intrinsic_metadata.egress_rid")
bit<16> egress_rid;
/// Indicates that a verify_checksum() method has failed.
/// 1 if a checksum error was found, otherwise 0.
bit<1> checksum_error;
/// Error produced by parsing
/// error parser_error;
/// set packet priority
@ALias("intrinsic_metadata.priority")
bit<6> priority;
}

struct ingress_metadata_t {
standard_metadata_t standard_metadata;
}

struct egress_metadata_t {
}

parser SwitchIngressParser(packet_in pkt, out Headers hdr, out ingress_metadata_t ig_md, out ingress_intrinsic_metadata_t ig_intr_md) {
state start {
transition accept;
}
}

control ingress(inout Headers h, inout ingress_metadata_t ig_md, in ingress_intrinsic_metadata_t ig_intr_md, in ingress_intrinsic_metadata_from_parser_t ig_prsr_md, inout ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md, inout ingress_intrinsic_metadata_for_tm_t ig_tm_md) {
action A1_Table1 () {
h.ethernet.dstAddr = 1;
}

table Table1 {
key = {
h.ethernet.etherType : exact;
}
actions = {
A1_Table1;
}
size=16000;
}

action A1_Table2 () {
h.ethernet.dstAddr = 1;
}
table Table2 {
key = {
h.ethernet.srcAddr : exact;
}
actions = {
A1_Table2;
}
size=1;
}
apply {
Table1.apply();
Table2.apply();
}
}
control SwitchIngressDeparser(packet_out pkt, inout Headers h, in ingress_metadata_t ig_md, in ingress_intrinsic_metadata_for_deparser_t ig_dprsr_md) {
apply {
pkt.emit(h);
}
}

parser SwitchEgressParser(packet_in pkt, out Headers h, out egress_metadata_t eg_md, out egress_intrinsic_metadata_t eg_intr_md) {
state start {
pkt.extract(eg_intr_md);
transition accept;
}
}

control SwitchEgress(inout Headers h, inout egress_metadata_t eg_md, in egress_intrinsic_metadata_t eg_intr_md, in egress_intrinsic_metadata_from_parser_t eg_intr_md_from_prsr, inout egress_intrinsic_metadata_for_deparser_t eg_intr_dprs_md, inout egress_intrinsic_metadata_for_output_port_t eg_intr_oport_md) {
apply {
}
}

control SwitchEgressDeparser(packet_out pkt, inout Headers h, in egress_metadata_t eg_md, in egress_intrinsic_metadata_for_deparser_t eg_intr_dprs_md) {
apply {
pkt.emit(h);
}
}

Pipeline(SwitchIngressParser(), ingress(), SwitchIngressDeparser(), SwitchEgressParser(), SwitchEgress(), SwitchEgressDeparser()) pipe;

Switch(pipe) main;

 

--------------------------------P4-14 program:--------------------------------

#include <tofino/intrinsic_metadata.p4>
#include "tofino/stateful_alu_blackbox.p4"

/* Declare Header */
header_type ethernet_t {
fields {
dstAddr : 48;
srcAddr : 48;
etherType : 16;
}
}

header ethernet_t ethernet;

parser start {
extract(ethernet);
return ingress;
}

action A1_Table1 () {
modify_field(ethernet.dstAddr, 1);
}

table Table1 {
reads {
ethernet.etherType : exact;
}
actions {
A1_Table1;
}
size:16000;
}

action A1_Table2 () {
modify_field(ethernet.dstAddr, 1);
}
table Table2 {
reads {
ethernet.srcAddr : exact;
}
actions {
A1_Table2;
}
size:1;
}

control ingress {
apply(Table1);
apply(Table2);
}

control egress {

}

0 Kudos
2 Replies
CrisselleF_C_Intel
Moderator
279 Views

Hello Xiangyu95,

 

Thank you for posting in Intel Communities. 

 

Unfortunately, your query is out of our scope. However, don't be concerned as we have a specific team who handles this query. Kindly visit the link below for FAQ: Transition Guide for BarefootNetworks.com Users and on how you can request a support. 

https://www.intel.com/content/www/us/en/products/network-io/barefoot-transition-faqs.html

 

You may also check this link and click on Contact us for further assistance.

https://www.intel.com/content/www/us/en/products/network-io/programmable-ethernet-switch.html#contac...

 

Please be informed that we will now close this request on our end. Just feel free to post a new question if you may have any other inquiry in the future as this thread will no longer be monitored.

 

Thank you for choosing Intel!

 

Best regards,

Crisselle C

Intel® Customer Support

 

Xiangyu95
Beginner
271 Views

Hello,

Thanks a lot for your reply. However, when I follow the Transition Guide forBarefootNetworks.com Users, it shows that I do not have access to the website: premiersupport.intel.com with the error message shown below. Is there anyone I should contact to apply for this access?

Thanks a lot again.

Xiangyu95_0-1610714155235.png

 

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