Initial Register Value

[Altera_Forum]

Hi Guys, 

I would like to ask the next question. The first one: Is it synthesizeable to determine value, such as 50000(integer), during reset (one step before "clk'event and clk..." line)?   *** if(reset = '1') then  conter <= 50000; elsif(clk'event and clk = '1') then ........ ........ ........ end if; ***  The second one: Is it synthesizeable to determine value, such as 50000(integer), as an initial value of the signal that declarated as an integer.  **** signal counter1 :integer range 0 to 50000 := 50000; ****  Thanks

[Altera_Forum]

Both methods should set the initial value of the register fine in Quartus.

[Altera_Forum]

Thanks for the quick reply, 

but when I enter the value during the reset state, it's work but sometimes FPGA doesn't respond at all. All processes are like a frozen. What can be the reason?  Tnx

[Altera_Forum]

Are you providing a reset signal to your FPGA? With the initial value you are sure that the design will power up with that value. If you set it in the reset state, it is only guaranteed to start with this value if you have an asserted reset signal in the FPGA.