Hello:
I'm new in verilog. Hopping that it's not a very stupid problem.
I'm tring to buid a FSM system using register "state" to perform the state now. There is no error hint or any functional problem on FSM insted of the initial problem on reg "state". The waveform shows that reg "state" keeping high at the begining, untill the stop signal arrives. Alought I had setting the initial value at begin, I can't fix it and I have no idea what could I do. Hopping that someone can help me.
Here is my code:
module state(start,stop,state);
input start,stop;
output reg state;
initial state = 1'b0;
always@(posedge start or posedge stop)begin
if(start == 1) state = 1;
else if(stop == 1) state = 0;
else state = state;
end
endmodule
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Hi,
I'm getting the desired vwf waveform for the code posted above. Check image below:
I think there is no problem with the code given.
File attached: fsm.zip
Quartus version: Prime 21.1 Standard Edition
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Sorry, I upload a wrong picture above. Here is my vwf waveform.
The "state" pin perform high at the begining. However, you said that the waveform simulation on your computer is correct. I'm wondering if it is because of the setting of my quartus. I just install Quartus these days. By the way, my quartus is version 13.1 web edition. I found that even I use timing simulation insted of functional simulation, there has no delay on the waveform. I'm not sure if there is a problem on the result and I'm figuring out the solution.
