We are using AGILEX AGIB027R31B2E2V FPGA .
For Implementing 100 G Ethernet we utilize 4 FHT lane (4x25) Bank 13C Rx / Tx rx/tx_serial port Lane 0 connected to FHTR13C RX/TX CH0 . When I implement the FPGA design I receive an error which seems to disappear when I use Lane0 For rx/tx_serial port (Inverse order) (0-1-2-3) => (3-2-1-0). We Finalized the PCB design so I want to learn If Lane reordering is handled in the IP core or not?
I have the same problem with interlaken IP. We use 12.5x12 Configuration (NRZ) and When I have the following connection on PCB. I get an error which disapper when I connect in reverse order (0:11) => (11:0) . I want to ask same question does Lane swapping automatically handled in IP?
FGTR13A_TX/RX_Q0_CH0 =Serial RX_Tx <0>
FGTR13A_TX/RX_Q0_CH1 =Serial RX_Tx <1>
FGTR13A_TX/RX_Q0_CH2 =Serial RX_Tx <2>
FGTR13A_TX/RX_Q0_CH3 =Serial RX_Tx <3>
FGTR13A_TX/RX_Q1_CH0 =Serial RX_Tx <4>
FGTR13A_TX/RX_Q1_CH1 =Serial RX_Tx <5>
FGTR13A_TX/RX_Q1_CH2 =Serial RX_Tx <6>
FGTR13A_TX/RX_Q1_CH3 =Serial RX_Tx <7>
FGTR13A_TX/RX_Q2_CH0 =Serial RX_Tx <8>
FGTR13A_TX/RX_Q2_CH1 =Serial RX_Tx <9>
FGTR13A_TX/RX_Q2_CH2 =Serial RX_Tx <10>
FGTR13A_TX/RX_Q2_CH3 =Serial RX_Tx <11>
The lane swapping is not automatically done in IP. The parameter has to be set to determine the kind of swapping that you're working on. Please refer Interlaken UG for more details.
How about 100 G Ethernet IP. Design including Ethernet IP implements when we have the reverse order. Can you comment on this ? Intel Dev Kits (Agilex I-Series Transceiver-SoC Development Kit) have different bit ordering for FHT implementations for different QSFP connectors.
FGTR13A_TX/RX_Q0_CH0 =Serial RX_Tx <3>
FGTR13A_TX/RX_Q0_CH1 =Serial RX_Tx <2>
FGTR13A_TX/RX_Q0_CH2 =Serial RX_Tx <1>
FGTR13A_TX/RX_Q0_CH3 =Serial RX_Tx <0>
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