Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19224 Discussions

Intel Cyclone 10 GX w. DDR3 Memory using PLL as Clock

RBibe
Beginner
197 Views

Hi,

can i use the internal PLL of Cyclone 10 GX instead of using dedicated Clock input for DDR3 memory Clock?

All Development boards are using a dedicated clock, so is this mandatory?

Thanks!

0 Kudos
3 Replies
Rahul_S_Intel1
Employee
131 Views

Hi ,

Kidnly follow the recommendation from the ug to connect to the clock to the emif Ip,

 

The PLL reference clock pin may be placed in the address and command I/O bank or in a data I/O bank, there is no implication on timing. 

 

Reference page no: 20

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf

Rahul_S_Intel1
Employee
131 Views

Hi ,

Kindly let me know if you need further assistance

RBibe
Beginner
131 Views

Dear Mr. Rahul,

 

thank you very much for your answer. Now its clear for me.

 

BR!

Reply