Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20866 Discussions

Intel Cyclone 10 GX w. DDR3 Memory using PLL as Clock

RBibe
Beginner
500 Views

Hi,

can i use the internal PLL of Cyclone 10 GX instead of using dedicated Clock input for DDR3 memory Clock?

All Development boards are using a dedicated clock, so is this mandatory?

Thanks!

0 Kudos
3 Replies
Rahul_S_Intel1
Employee
434 Views

Hi ,

Kidnly follow the recommendation from the ug to connect to the clock to the emif Ip,

 

The PLL reference clock pin may be placed in the address and command I/O bank or in a data I/O bank, there is no implication on timing. 

 

Reference page no: 20

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf

0 Kudos
Rahul_S_Intel1
Employee
434 Views

Hi ,

Kindly let me know if you need further assistance

0 Kudos
RBibe
Beginner
434 Views

Dear Mr. Rahul,

 

thank you very much for your answer. Now its clear for me.

 

BR!

0 Kudos
Reply