can i use the internal PLL of Cyclone 10 GX instead of using dedicated Clock input for DDR3 memory Clock?
All Development boards are using a dedicated clock, so is this mandatory?
Kidnly follow the recommendation from the ug to connect to the clock to the emif Ip,
The PLL reference clock pin may be placed in the address and command I/O bank or in a data I/O bank, there is no implication on timing.
Reference page no: 20