I am working on a gate driver design using the Intel MAX 10 10M08SAU169I7G. The FPGA is driving the signals G1_high and G1_high_inv in the attached schematic. The supply rail available (so far) is 3.3V. At this voltage I can select drive strengths 2mA for LVCMOS and 8mA for LVTTL. If I reduce the voltage to 3.0V, I can select drive strength 16mA for both LVCMOS and LVTTL. I have been able to translate the IBIS models to spice.
- CMOS is faster than LVTTL at the same voltage(3.0V) + drive strength (16mA).
- 16mA is faster than 8mA at the same voltage (3.0V)
- Can I safely configure the outputs as 3.0V LVCMOS 16mA outputs with VCC=3.3V if this gives me the best results in my circuit?
- If this is not safe, what would go wrong? The toggle rate is low (1.5kHz) so there will be no problem with heat.
- I assume that the limitation in drive strength for the IO standards is due to the fact that the output pin will not be able to drive the output at the wanted drive strength and meet the IO standard requirements (VCC-0.2V for LVCMOS). Please elaborate?
- Is there any real difference in the IO buffer between LVCMOS and LVTTL for the same voltage + drive strengths?
- What would be my best option in your opinion to speed up this gate driver stage?