The customer is using either an Altera Cyclone part or a Critical Link board with Cyclone on it. This question came in from Critical Link regarding PCIe timing.
A customer use the MitySOM-5CSX SOM, and are wondering if they need to have a common reference clock between end points and root port for PCIe. Through Intel's docs I couldn't find a clear answer to this, I think my question can be summed up in the following:
Does the Cyclone V SX supports Separate Reference Clock No Spread Spectrum (SRNS) and/or Separate Reference Clock with Independent Spread Spectrum (SRIS)?
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Thanks for make this question more clear.
If refer to latest version of user guide "V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide"
under C. Document Revision History, it mention that
"Mentioned in the Features section that this IP supports the Separate Reference Clock No Spread Spectrum (SRNS) architecture and not the Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture."
Hope this clarified. Regards,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
We have not hear from you and this Case is idling. It is not recommended to idle for too long.
Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience caused
Hence, This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
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