I have set up a TTK link between a board with a Cyclone V and another board with Arria 10. I have a stable CDR lock in both directions but when I start data transmission, it fails in both directions with slightly different behavior.
From Arria to Cyclone, the number of transmitted bits stays at zero.
From Cyclone to Arria, the number of transmitted bits increments, but the BER is constantly high.
I use PRBS7. I wonder if this could be a word alignment issue? Does TTK handle word alignment automatically or do I have to implement something explicitly?
When I make a feedback in hardware for the same physical link, and test with TX and RX on the same device, I always get zero BER.
Best regards, Julia
As I understand it, you observe some problems when trying to perform a link BER test between CV TTK and A10 TTK. Based on your description, one of the possible reasons might be the patterns between the CV TTK is not directly compatible with the A10 TTK. Sorry as I do not have the visibility into data transmitted from the TTKs but this is just a suspect.
As a workaround, you may create simple test design with PRBS generator and checker. Run the BER test and monitor using signaltap. You may in parallel use the TTKs to dynamically tune analog settings on both device and monitor the BER in signaltap.
Please let me know if there is any concern. Thank you.
Thanks for your update. I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.