I am using the CycloneV device.
I use logiclock to fix placement position in the same LAB. But when I set different input delays, routing at the same position produces different results.
This path is the path directly from the I/O pad to the first register.
As shown in fig,
Is there any way that I can limit the delay range of this IC?
That's kind of the point of set_input_delay. The larger value you give for -max, the more time the router has to play with, so it may add more routing between the I/O and the input register. What is your goal here and what does your .sdc look like?
Thank you for your help,
I have 12 different data input from 12 I/O pads, and they will enter 12 different input first register respectively.
I use logiclock to keep all registers close to their own I/O pads.
But the data delay of each path has a big gap, I want to know how can I make their values closer.
First of all, don't use Logic Lock. Rely on your set_input_delay constraints to have the registers placed close to the I/O by the Fitter. You could also use the Fast Input Register assignment to make use of the registers right in the I/O element. Second, there are some additional constraints (like set_data_skew I think) that you could use if you're trying to do matching. I'm not super familiar with using them so somebody else could chime in on that.
I still don't have any idea about the correct adjustment of the timing.
Quatus seems to synthesize paths that I think should have the same phenomenon into different delays.
So I'm going to look for other ways to fix this issue.
Thank you very much for your reply.
Understood. With that, I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.